(a) Fields of the Invention
The present invention relates to semiconductor integrated circuits made by integrating a great number of MIS transistors.
(b) Description of Related Art
With rapid miniaturization of semiconductor integrated circuits, layout pattern, arrangement, and the like of circuit elements have been diversified and complicated in system LSIs (Large Scale Integrations) and the like. Because of this trend, in development of such system LSIs, it becomes difficult to improve the simulation accuracy of a circuit simulator.
Typically, from a mask layout of a designed cell, information on connection between elements such as transistors, capacitors, and resistors, and in addition information on element characteristics such as transistor size, parasitic capacitance, parasitic resistance, and the like are extracted as a net list using a layout parameter extraction (abbreviated hereinafter as “LPE”) of a circuit, and the extracted information is reflected to the circuit simulator. Complicated transistor-characteristic information is modeled in the form of an electric characteristic equation using model parameters of the transistors extracted from the mask layout, and the modeled information is reflected to a circuit simulator. This offers a highly accurate simulation.
However, with recent miniaturization of elements, a problem has arisen that a large characteristic difference occurs between an ideal single transistor used to extract model parameters and a CMOS (Complementary Metal Oxide Semiconductor)-type transistor arranged in a cell widely used in actual design. One of such problems includes characteristic fluctuation of a transistor resulting from the well proximity effect.
In the CMOS structure, an n-type well and a p-type well are formed in a single substrate, and elements such as a p-channel type MISFET (Metal-Insulator-Semiconductor Field Effect Transistor) and an n-channel type MISFET are formed thereon. In this structure, the well regions are formed so that the regions other than the well regions are covered with a photoresist and then using this photoresist as a mask, ions with high energies are implanted into the substrate.
During this implantation, some of impurity ions implanted at high energies scatter within the photoresist, and are emitted from the photoresist and then implanted into the well regions. As a result of this, if the MISFET is formed at an end of the well region, the impurity ions scattered within the photoresist affect the MISFET to fluctuate the threshold voltage thereof (see, for example, Japanese Unexamined Patent Publication No. 2005-150731). This phenomenon is called the well proximity effect.
In order to reduce the influence of the well proximity effect, technical development is being made for the purpose of modeling characteristic fluctuation by the well proximity effect and reflecting the modeled one to a circuit simulator. However, it is feared that such reflection of the modeled characteristic fluctuation to the circuit simulator increases simulation time and development time. Furthermore, the range affected by the well proximity effect is as large as several micrometers, so that highly accurate modeling within realistic simulation time is difficult. This will be described a little more specifically.
Recent system LSIs have been designed by cell-based design methods. FIG. 8 is a plan view showing an example of a conventional cell constituting a system LSI. The transistor arrangement in the cell varies according to functions and applications of a logic circuit configured by the cell, and a plurality of cells as shown in FIG. 8 are used in combination to design the system LSI.
In the conventional example shown in FIG. 8, p-type active regions POD14 and POD15 having gate widths of Wp14 and Wp15, respectively, are arranged in an n-type well NW7 formed in a semiconductor substrate 101. Also, n-type active regions NOD14 and NOD15 having gate widths of Wn14 and Wn15, respectively, are arranged in a p-type well PW7 formed in the semiconductor substrate 101. Gate interconnects GA14 and GA15 are formed above the p-type active regions POD14 and POD15 and the n-type active regions NOD14 and NOD15, respectively. P-channel transistors PTr14 and PTr15 and n-channel transistors NTr14 and NTr15 composed of these respective components are arranged in the cell. Letting WELL7 denote the boundary between the n-type well NW7 and the p-type well PW7 (abbreviated hereinafter as “the well boundary”), in PTr14, the distance from WELL7 to the end of POD14 is represented as STIp14, and in NTr14, the distance from WELL7 to the end of NOD14 is represented as STIn14. Likewise, in PTr15, the distance from WELL7 to the end of POD15 is represented as STIp15, and in NTr15, the distance from WELL7 to the end of NOD15 is represented as STIn15. Thus, the calculated distance of PTr14 from the well boundary is represented as (STIp14+0.5×Wp14), the calculated distance of NTr14 from the well boundary is represented as (STIn14+0.5×Wn14), the calculated distance of PTr15 from the well boundary is represented as (STIp15+0.5×Wp15), and the calculated distance of NTr15 from the well boundary is represented as (STIn15+0.5×Wn15).
In this configuration, in the transistors with the active regions having different gate widths, the distances from the well boundary to the centers of the active regions in the gate width direction satisfy the following relations:(STIp14+0.5×Wp14)≠(STIp15+0.5×Wp15)  (1)(STIn14+0.5×Wn14)≠(STIn15+0.5×Wn15)  (2)
It is known that the amount of change in the threshold voltage of the transistor due to impurity concentration change associated with the well proximity effect is proportional to the square root of the impurity concentration and thus an increase in the impurity concentration caused by the well proximity effect is inversely proportional to the distance from the well boundary. As shown in the above expressions (1) and (2), since the transistors differ in the distance from the well boundary to the center of the active region in the gate width direction, characteristic fluctuation affected by the well proximity effect also differs among the transistors. Circuit simulation taking the well proximity effect into consideration can be performed. However, with this simulation, it is difficult to evaluate the transistor characteristics in a short time, which is likely to cause lengthening of development time and an increase in development cost.